The high conversion efficiency of silicon rectifiers for DC output ratings above 30 volts has resulted in substantial savings in power costs. However, silicon failures in high lightning incidence areas and on power supply lines with poor control of switching transients have been unacceptably high. Peak inverse voltage failures of silicon can be caused by lightning induced transients in either the supply lines or in the CP loop without a direct strike. Silicon and selenium failure rates by areas are compared with a Bureau of Standards lightning incidence rate map. Data covering the variation of CP loop resistance from dry anode bed to moist soil condition confirms the wisdom of secondary over-current protection. A magamp circuit which controls DC current within plus or minus 2 percent with loop resistance varying from .6 to 2.5 ohms is discussed. Present and future developments to protect silicon against PIV failures are discussed.
5.2.3
